Novel CMOS circuit of GaAs/Ge on Si substrate

ABSTRACT

A GaAs/Ge on Si CMOS integrated circuit is formed to improve transistor switching (propagation) delay by taking advantage of the high electron mobility for GaAs in the N-channel device and the high hole mobility for Ge in the P-channel device. A semi-insulating (undoped) layer of GaAs is formed over a silicon base to provide a buffer layer eliminating the possibility of latch-up. GaAs and Ge wells are then formed over the semi-insulating GaAs layer, electrically isolated by standard thermal oxide and/or flowable oxide (HSQ). N-channel MOS devices and P-channel MOS devices are formed in the GaAs and Ge wells, respectively, and interconnected to form the integrated circuit. Gate electrodes for devices in both wells may be polysilicon, while the gate oxide is preferably gallium oxide for the N-channel devices and silicon dioxide for the P-channel devices. Minimum device feature sizes may be 0.5 μm to avoid hot carrier degradation while still achieving performance increases over 0.18 μm silicon-only CMOS integrated circuits.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates generally to integrated circuitdevice fabrication employing multiple semiconductor materials, and morespecifically to integration of distinct semiconductor materials selectedto optimize the speed of an integrated circuit including devices formedwithin each of the semiconductor materials.

[0003] 2. Description of the Prior Art

[0004] Materials and device physics for commercial solid statesemiconductor device fabrication have progressed through a wide spectrumof materials, material combinations, and device structures. Startingwith the Germanium (Ge) point contact transistor in 1948, developmentsprogressed in the 1950s through single-crystal Ge devices, Ge bipolarjunction transistors (BJTs), Ge junction field effect transistors(JFETs), single crystal silicon (Si) devices, and silicon bipolarjunction transistors. After development of silicon planar bipolarjunction transistors and silicon metal oxide semiconductor field effecttransistors (MOSFETs) in the early 1960s, together with Gallium Arsenide(GaAs) devices a few years later, progress on use of specific materialsslowed until the latter half of the 1980s, with development of GaAs onSi devices and SiGe/Si heterojunction bipolar transistors (HBTs). Inthis decade, development of materials technology in semi-conductordevice fabrication has progressed from GaAs on Si and SiGe/Si throughGaAs metal semiconductor field effect transistors (MESFETs), Sicomplementary metal oxide semiconductor (CMOS) devices, SiGe/Si metaloxide semiconductor (MOS) devices, Aluminum GalliumArsenide-Germanium-Gallium Arsenide (AlGaAs/Ge/GaAs) HBTs, and GaAs MOSdevices.

[0005] For at least a decade, silicon MOS and CMOS technologies havebeen the mainstay of commercial semiconductor device fabrication, withadvances in device feature size into the submicron range providingimprovements in device performance. As very large scale integration(VLSI) technology pushes toward smaller geometries, however, thetransistor channel length and the parasitic resistive-capacitive (RC)constant finally limit circuit speed. The transistor switching(propagation) delay t_(pd) of a CMOS device, which is a function of thedevice load capacitance, the drain voltage, and the saturation currentsfor both the n-channel and p-channel devices, limit the maximumoperating frequency for an integrated circuit device.

[0006] Improvement of performance in contemporary silicon MOS and CMOSprocesses through reduction of feature sizes, which are already lessthan 0.18 μm for CMOS channel lengths, is becoming increasinglydifficult. Additionally, the electrical properties of silicon itself,particularly charge carrier mobility, are an increasingly significantlimitation of device performance. For shorter device channel lengths,for example, carrier mobility (μ, typically expressed in units ofcm²/V×sec) becomes an increasingly contributor to propagation delay.Accordingly, different combinations of semiconductor materials havingdifferent, beneficial electrical characteristics—such as SiGe—arecurrently being explored.

[0007] It would be desirable, therefore, to improve circuit speed insemiconductor integrated circuits, particularly through use ofcommercially viable materials and processing technology. It wouldfurther be advantageous to employ distinct semi-conductor materials totake advantage of the best electrical properties of different materials.

SUMMARY OF THE INVENTION

[0008] A GaAs/Ge on Si CMOS integrated circuit is formed to improvetransistor switching (propagation) delay by taking advantage of the highelectron mobility for GaAs in the N-channel device and the high holemobility for Ge in the P-channel device. A semi-insulating (undoped)layer of GaAs is formed over a silicon base to provide a buffer layer,significantly lessening the possibility of latch-up. GaAs and Ge wellsare then formed over the semi-insulating GaAs layer, electricallyisolated by standard thermal oxide and/or flowable oxide (HSQ).N-channel MOS devices and P-channel MOS devices are formed in the GaAsand Ge wells, respectively, and interconnected to form the integratedcircuit. Gate electrodes for devices in both wells may be polysilicon,while the gate oxide is preferably gallium oxide for the N-channeldevices and silicon dioxide for the P-channel devices. Minimum devicefeature sizes may be 0.5 μm to avoid hot carrier degradation while stillachieving performance increases over 0.18 μm silicon-only CMOSintegrated circuits.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The novel features believed characteristic of the invention areset forth in the appended claims. The invention itself however, as wellas a preferred mode of use, and further objects and advantages thereof,will best be understood by reference to the following detaileddescription of an illustrative embodiment when read in conjunction withthe accompanying drawings, wherein:

[0010] FIGS. 1A-1E depict a series of cross-sections for a process offorming a GaAs/Ge on Si CMOS integrated circuit in accordance with apreferred embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0011] The following description details the structure, application andfeatures of the present invention, but it will be understood by those ofskill in the art that the scope of the invention is defined only by theissued claims, and not by any description herein. The process steps andstructures described below do not form a complete process flow formanufacturing integrated circuits. The present invention can bepracticed in conjunction with common integrated circuit fabricationtechniques, and only so much of the commonly practiced process steps areincluded as are necessary for an understanding of the present invention.The figures representing cross-sections of portions of an integratedcircuit during fabrication are not drawn to scale, but instead are drawnso as to illustrate the important features of the invention.

[0012] The present invention improves circuit speed by reducingpropagation delay t_(pd), which may be calculated for a typical CMOSring oscillator from:$t_{pd} = {{0.27 \cdot C_{L}}{V_{DD}\left( \frac{I_{dsatn} + I_{dsatp}}{I_{dsatn}I_{dsatp}} \right)}}$

[0013] where C_(L) is the load capacitance, V_(DD) is the drain voltage,I_(dsatn) is the N-channel transistor saturation current, and I_(dsatp)is the P-channel transistor saturation current. Since I_(dsatn) andI_(dsatp) are proportional to the electron mobility μ_(n) and the holemobility μ_(p), respectively, the above expression for transistorswitching or propagation delay may be rewritten as:$t_{pd} = {A\left( \frac{\mu_{n} + \mu_{p}}{\mu_{n}\mu_{p}} \right)}$

[0014] where A is a constant related to the doping level in thechannels, the load capacitance, and the drain voltage.

[0015] It is well known that the speed of 0.18 μm Si CMOS integratedcircuits is limited by the P-type MOS (PMOS) transistor. In order toovercome this limit, the present invention employs distinctsemiconductor materials in the CMOS integrated circuit selected forelectrical properties which optimize circuit speed. As used herein,“semiconductor material” refers to a chemical species of semiconductor,such as Si, Ge, or GaAs, as distinct from a “type” of semiconductor,which refers to the dopant type (i.e., N-type or P-type). Sincepropagation delay may be viewed as a function of electron and holemobility, semiconductor materials are selected for the present inventionwhich improve switching speed over silicon CMOS integrated circuits,where the improvement is characterized by a speed (improvement) factor Sgiven by: $S = \left( \frac{t_{pd}({Si})}{t_{pd}(M)} \right)$

[0016] where t_(pd)(Si) is the propagation delay for a silicon CMOSintegrated circuit and t_(pd)(M) is the propagation delay for a similarCMOS integrated circuit employing the selected material(s) M. Table Ibelow lists the electron and hole mobilities for different materials ormaterial combinations which might be employed in a CMOS integratedcircuit, together with the resulting speed improvement factor S. TABLE ISpeed Mobility (drift) Improvement (cm²/V-s) Factor Material(s) μ_(n)μ_(p) (S) Si 1500 450 1 Ge 3900 1900 3.7 GaAs 8500 400 1.1 Si/Ge 15001900 2.4 GaAs/Ge 8500 1900 4.5

[0017] The mobility values μ_(p) and μ_(p) in Table I are taken from S.M. Sze, Physics of Semiconductor Devices, John Wiley & Sons (New York1981). The values for speed improvement factor S in Table I areapproximated from the mobility values, neglecting any material-specificdifferences for constant A.

[0018] It may be readily seen from Table I that the electron mobility ofGaAs is higher than that of Si by more than 5 times, and the holemobility of Ge is higher than that of Si by over 4 times. Sinceelectrons are the majority charge carrier in NMOS devices while holesare the majority charge carrier in PMOS devices, the combination ofGaAs-NMOS and Ge-PMOS will have the highest CMOS integrated circuitspeed. Therefore, a novel CMOS integrated circuit structure utilizingGaAs/Ge CMOS on a Si substrate is employed in the present invention,optimizing circuit speed by employing GaAs for electron mobility and Gefor hole mobility. In a ring oscillator employing this GaAs/Ge on SiCMOS circuit, the propagation delay t_(pd) is shorter than that of anordinary Si CMOS circuit by a multiple of 3.5, meaning that 1.0 μmtechnology implemented in GaAs/Ge on Si can reach approximately the sameperformance as 0.25 μm technology implemented in silicon only.

[0019] With reference now to the figures, and in particular withreference to FIGS. 1A through 1E, a series of cross-sections for aprocess of forming a GaAs/Ge on Si CMOS integrated circuit in accordancewith a preferred embodiment of the present invention are depicted. Theprocess of the present invention begins with the structure shown in FIG.1A, which includes a substrate 102. In the preferred embodiment,substrate 102 includes a silicon region 102 a having a thickness ofapproximately 10-15 mils (roughly 250-400 μm), providing structuralintegrity and grounding for the CMOS circuit to be formed. Siliconregion 102 a may be doped with a P-type dopant, if desired. The dopantlevels should be selected for the particular fabrication process(es)employed and device performance criteria sought in accordance with knowntechniques. Over the silicon region 102 a is a semi-insulating galliumarsenide layer 102 b having a thickness of less than 50,000 Å (5 μm),and more preferably in the range of 20,000 to 30,000 Å (2-3 μm). GaAslayer 102 b may be undoped, and may be formed by metal organic chemicalvapor deposition (MO CVD), molecular beam epitaxy (MBE) or othersuitable process as appropriate. GaAs layer 102 b provides a bufferlayer on the Si region 102 a, substantially eliminating the possibilityof latch-up. Substrate 102, with a structure of the type described above(20,000-30,000 Å of undoped GaAs 102 b on Si 102 a), is commerciallyavailable.

[0020] An active GaAs layer 104 is formed on substrate 102. GaAs layer104 preferably has a thickness of less than or equal to 2 μm, may bedoped with a P-type dopant or dopants, and may be formed by chemicalvapor deposition (CVD) or molecular beam epitaxy (MBE) in a mannersimilar to formation of GaAs layer 102 b, or by other suitable process.GaAs layer 104 is then patterned and etched, utilizing conventionalmethods, to form a P-type GaAs well 106 as shown in FIG. 1B, in whichNMOS devices will be formed. The high breakdown field of the GaAsreduces hot carrier degradation of NMOS devices formed within GaAs well106. Again, the doping levels, and the particular methods employed forachieving the doping (e.g., during formation of the N and P wells, orafter), may be selected from known parameters and techniques to achievedesired performance characteristics.

[0021] A Ge layer 108, doped with N-type dopants, is formed over theGaAs well 106 and GaAs buffer layer 102 b to a thickness equal to orgreater than the thickness of GaAs well 106. As with GaAs layer 104, Gelayer 108 may be formed by MO CVD or MBE processes; Ge layer 108 mayalso be formed by another CVD process or possibly by selectivedeposition or other suitable process. As illustrated by alternateprofile 108 a, Ge layer 108 may be formed as a conformal layer whendeposited by MO CVD or MBE, then planarized, for example, bychemical-mechanical polishing (CMP). The planarization etch ispreferably stopped when the upper surface of GaAs well 106 is exposed,and the thickness of the remaining Ge layer 108 is equal to thethickness of GaAs well 106. Preferably only a little, if any, of GaAswell 106 is removed in planarizing Ge layer 108. Ge layer 108 ispatterned and etched, utilizing conventional methods, to form a Ge well110, laterally spaced apart from GaAs well 106 on the surface ofsubstrate 102 as shown in FIG. 1C, in which PMOS devices will be formed.

[0022] Isolation regions 112 are then formed between the GaAs well 106and the Ge well 110, and between GaAs well 106 or Ge well 110 andadjacent regions (not shown), preferably through the use of flowableoxide (FOX), or hydrogen silsesquioxane (HSQ). The FOX is formed overthe entire surface of the substrate, over GaAs well 106 and Ge well 110,and between and otherwise adjacent to GaAs well 106 and Ge well 110. TheFOX is formed with a substantially planar upper surface, with athickness greater than the thickness of GaAs well 106 and Ge well 110.The FOX is then etched back to expose the upper surfaces of GaAs well106 and Ge well 110. Etch stop layers (not shown) may optionally beformed over GaAs well 106 and Ge well 110 prior to formation of the FOX,then removed after the FOX has been etched back to a desired thickness.

[0023] At least a portion 112 a of any isolation oxide region 112 mayoptionally be a thermal oxide, a deposited oxide, or some otherdielectric. For a thermal oxide portion 112 a, the oxide may be grownafter the formation of GaAs well 106 and Ge well 110 but beforeformation of an overlying FOX. Similarly, a deposited oxide or otherdeposited dielectric region may be deposited after formation of GaAs andGe wells 106 and 110 but before formation of an overlying FOX layer.Isolation oxide may be formed of any number of dielectric layers andmaterials between and around GaAs and Ge wells 106 and 110. The combinedthickness of such dielectric layers and materials is preferably lessthan the thickness of GaAs and Ge wells 106 and 110, and a FOX layer ispreferably formed over all such dielectric layers and materials asdescribed above, then etched back until the upper surface of isolationregions 112 are substantially planar with the upper surfaces of GaAs andGe wells 106 and 110.

[0024] For a CMOS device, at least one NMOS device 114 is formed withinGaAs well 106, and at least one PMOS device 116 is formed within Ge well110, as shown in FIG. 1D. NMOS and PMOS devices 114 and 116 may bothinclude conventionally formed source/drain regions 118, 120, formed, forexample, by diffusion and/or implantation, and lightly dopedsource/drain regions 122, 124. Source/drain regions 118 and lightlydoped source/drain regions 122 for NMOS device 114 are doped with N-typedopants, while source/drain regions 120 and lightly doped source/drainregions 124 for PMOS device 116 are doped with P-type dopants. NMOSdevice 114 includes a gate dielectric 126. The gate dielectric 126 forNMOS device 114 is preferably gallium oxide (GaO_(x)), which may bethermally grown or deposited to a thickness selected for desired deviceperformance. PMOS device 116 includes a gate dielectric 128. The gatedielectric 128 for PMOS device 116 is preferably silicon dioxide (SiO₂),which may be formed by conventional methods (e.g., deposited) with athickness selected for desired device performance. Gate electrodes 130for both NMOS and PMOS devices 114 and 116 may be polysilicon, andsidewalls 132 for both devices may be conventional tetraethoxysilane(TEOS) dielectric sidewall structures or other appropriate materials.

[0025] In forming NMOS and PMOS devices 114 and 116, a minimum devicefeature size of 0.5 μm is preferably employed to avoid hot carrierdegradation, although smaller feature size may be employed to improvedevice density and more efficiently utilize chip area. Due toimprovements is speed, however, overall performance obtainable only with0.18 μm minimum device feature sizes in silicon-only CMOS integratedcircuits may be maintained with the present invention utilizing minimumfeature sizes of 0.5 μm. Where performance degradation from hot carrierinjection may be avoided, smaller feature sizes may be utilized in thepresent invention to further improve speed.

[0026] After NMOS and PMOS devices 114 and 116 have been formed, a layeror several layers of insulation or passivation material 134 such asborophosphosilicate glass (BPSG) is formed over the devices 114 and 116as depicted in FIG. 1E, together with any other metallization,insulation, or passivation layers (not shown) which are required to forma complete integrated circuit. Although only one NMOS device 114 and onePMOS device 116 are shown in the exemplary embodiment as being formedwithin GaAs well 106 and Ge well 110, those skilled in the art willrecognize that GaAs well 106 and Ge well 110 are elongate, shown only incross-section, and may contain any number of NMOS or PMOS devices. Thesedevices may be connected by interconnects within various metallizationlevels to form any integrated circuit.

[0027] Those skilled in the art will also recognize that variations inthe order of portions of the process described above are possible. Forexample, NMOS device 114 may be formed within GaAs well 106 prior toformation of Ge layer 108. This would be especially useful if utilizedto leave a Ge cover layer over the upper surface of NMOS source/drainregions 118, for making contact between source/drain regions 118 andoverlying metallization (not shown). Together with a titanium/germaniumcontact, such a Ge cover layer could reduce Ohmic contact resistanceand, in turn, further increase circuit speed.

[0028] The present invention reduces transistor propagation delay andimproves integrated circuit speed by implementing CMOS circuits in aGaAs/Ge on Si structure, taking advantage of the electron mobility forGaAs and the hole mobility for Ge. A semi-insulating GaAs buffer layerbetween the silicon base of the substrate and the GaAs and Ge devicewells substantially eliminates the possibility of latch-up. Flowableoxide or other insulating material between wells provides requisitelateral electrical isolation.

[0029] While the invention has been particularly shown and describedwith reference to a preferred embodiment, it will be understood by thoseskilled in the art that various changes in form and detail may be madetherein without departing from the spirit and scope of the invention.

What is claimed is:
 1. A structure for forming a CMOS integratedcircuit, comprising: a gallium arsenide region on a substrate; and agermanium region on the substrate, the germanium region electricallyisolated from the gallium arsenide region.
 2. The structure of claim 1,wherein the gallium arsenide region and the germanium region areapproximately equal in thickness.
 3. The structure of claim 2, whereinthe gallium arsenide region and the germanium region have a thicknessless than or equal to about 2 μm.
 4. The structure of claim 1, whereinthe gallium arsenide region is formed by deposition of a galliumarsenide layer on the substrate and removal of portions of the galliumarsenide layer, leaving the gallium arsenide region.
 5. The structure ofclaim 4, wherein the gallium arsenide layer is formed by MO CVD or MBE.6. The structure of claim 1, wherein the germanium region is formed bydeposition of a germanium layer on the substrate and over the galliumarsenide region and removal of portions of the germanium layer to leavethe germanium region.
 7. The structure of claim 6, wherein the germaniumlayer is formed by MO CVD or MBE.
 8. The structure of claim 6, whereinchemical mechanical polishing is utilized to remove portions of thegermanium layer over the gallium arsenide region.
 9. The structure ofclaim 1, wherein the substrate further comprises: a buffer layer onwhich the gallium arsenide region and the germanium region are formed.10. The structure of claim 9, wherein the substrate further comprises: asilicon base on which the buffer layer is formed, wherein the bufferlayer is a semi-insulating gallium arsenide layer.
 11. The structure ofclaim 1, further comprising: an isolation region on the substratebetween the gallium arsenide region and the germanium region.
 12. Thestructure of claim 11, wherein the gallium arsenide region, thegermanium region, and the isolation region are approximately equal inthickness.
 13. The structure of claim 11, wherein the isolation regionis formed from flowable oxide deposited on the substrate and over thegallium arsenide region and the germanium region then etched back toexpose upper surfaces of the gallium arsenide region and the germaniumregion.
 14. The structure of claim 11, wherein the isolation region isformed by: growing a thermal oxide on the substrate between the galliumarsenide region and the germainum region; depositing a flowable oxideover the thermal oxide, the gallium arsenide region, and the germaniumregion; and etching the flowable oxide to expose upper surfaces of thegallium arsenide region and the germanium region.
 15. A CMOS integratedcircuit, comprising: a substrate; a gallium arsenide region on thesubstrate; a germanium region on the substrate, the germanium regionelectrically isolated from the gallium arsenide region; at least oneN-channel device in the gallium arsenide region; and at least oneP-channel device in the germanium region, the at least one N-channeldevice and the at least one P-channel device electrically connected toform a circuit.
 16. The integrated circuit of claim 15, wherein thesubstrate further comprises: a silicon base; and a semi-insulatinggallium arsenide buffer layer over the silicon base, wherein the galliumarsenide and germanium regions are formed on the semi-insulating galliumarsenide buffer layer.
 17. The integrated circuit of claim 15, furthercomprising: oxide regions on the substrate between the gallium arsenideand germanium regions and between the gallium arsenide region or thegermanium region and an adjacent region.
 18. An integrated circuitstructure, comprising: a substrate comprising a first semiconductormaterial; a first well for N-channel devices formed on the substrate andcomprising a second semiconductor material different than the firstsemi-conductor material; and a second well for P-channel devices formedon the substrate and comprising a third semiconductor material differentthan the first and second semiconductor materials.
 19. The integratedcircuit structure of claim 18, wherein the substrate comprises P-typesilicon and undoped gallium arsenide over the P-type silicon, the firstwell comprises P-type gallium arsenide, and the second well comprisesN-type germanium.
 20. The integrated circuit structure of claim 18,wherein the second semiconductor material is selected for electronmobility and the third semiconductor material is selected for holemobility.
 21. The integrated circuit structure of claim 18, wherein thesecond semiconductor material is a first chemical species ofsemiconductor and the third semiconductor material is a second chemicalspecies of semiconductor different from the first chemical species ofsemiconductor.
 22. A method of forming a CMOS integrated circuit,comprising: forming a gallium arsenide region on a substrate; andforming a germanium region on the substrate, the germanium regionelectrically isolated from the gallium arsenide region.
 23. The methodof claim 22, further comprising: forming the gallium arsenide region andthe germanium region to be approximately equal in thickness.
 24. Themethod of claim 23, wherein the step of forming the gallium arsenideregion and the germanium region to be approximately equal in thicknessfurther comprises: forming the gallium arsenide region and the germaniumregion to a thickness of less than or equal to about 2 μm.
 25. Themethod of claim 22, wherein the step of forming a gallium arsenideregion on a substrate further comprises: depositing a gallium arsenidelayer on the substrate; and removing portions of the gallium arsenidelayer, leaving the gallium arsenide region.
 26. The method of claim 25,wherein the step of depositing a gallium arsenide layer on the substratefurther comprises: forming the gallium arsenide layer by MO CVD or MBE.27. The method of claim 22, wherein the step of forming a germaniumregion on the substrate further comprises: depositing a germanium layeron the substrate and over the gallium arsenide region; and removingportions of the germanium layer to leave the germanium region.
 28. Themethod of claim 27, wherein the depositing a germanium layer on thesubstrate and over the gallium arsenide region further comprises:forming the germanium layer by MO CVD or MBE.
 29. The method of claim27, wherein the step of removing portions of the germanium layer toleave the germanium region further comprises: removing portions of thegermanium layer over the gallium arsenide region by chemical mechanicalpolishing.
 30. The method of claim 22, further comprising: forming abuffer layer on which the gallium arsenide region and the germaniumregion are formed.
 31. The method of claim 30, wherein the step offorming a buffer layer on the substrate on which the gallium arsenideregion and the germanium region are formed further comprises: forming asemi-insulating gallium arsenide layer on a silicon base.
 32. The methodof claim 22, further comprising: forming an isolation region on thesubstrate between the gallium arsenide region and the germanium region.33. The method of claim 32, further comprising: forming the galliumarsenide region, the germanium region, and the isolation region toapproximately a same thickness.
 34. The method of claim 32, wherein thestep of forming an isolation region on the substrate between the galliumarsenide region and the germanium region further comprises: depositingflowable oxide on the substrate and over the gallium arsenide region andthe germanium region; and etching the flowable oxide to expose uppersurfaces of the gallium arsenide region and the germanium region. 35.The method of claim 32, wherein the step of forming an isolation regionon the substrate between the gallium arsenide region and the germaniumregion further comprises: growing a thermal oxide on the substratebetween the gallium arsenide region and the germainum region; depositinga flowable oxide over the thermal oxide, the gallium arsenide region,and the germanium region; and etching the flowable oxide to expose uppersurfaces of the gallium arsenide region and the germanium region.
 36. Amethod of forming a CMOS integrated circuit, comprising: forming agallium arsenide region on a substrate; forming a germanium region onthe substrate, the germanium region electrically isolated from thegallium arsenide region; forming at least one N-channel device in thegallium arsenide region; and forming at least one P-channel device inthe germanium region, the at least one N-channel device and the at leastone P-channel device electrically connected to form a circuit.
 37. Themethod of claim 36, further comprising: forming a semi-insulatinggallium arsenide buffer layer over a silicon base, wherein the galliumarsenide and germanium regions are formed on the semi-insulating galliumarsenide buffer layer.
 38. The method of claim 36, further comprising:forming oxide regions on the substrate between the gallium arsenide andgermanium regions and between the gallium arsenide region or thegermanium region and an adjacent region.
 39. A method of forming anintegrated circuit structure, comprising: providing a substratecomprising a first semiconductor material; forming a first well forN-channel devices formed on the substrate and comprising a secondsemiconductor material different than the first semi-conductor material;and forming a second well for P-channel devices formed on the substrateand comprising a third semiconductor material different than the firstand second semiconductor materials.
 40. The method of claim 39, whereinthe substrate comprises P-type silicon and undoped gallium arsenide overthe P-type silicon, the first well comprises P-type gallium arsenide,and the second well comprises N-type germanium.
 41. The method of claim39, wherein the second semiconductor material is selected for electronmobility and the third semiconductor material is selected for holemobility.
 42. The method of claim 39, wherein the second semiconductormaterial is a first chemical species of semiconductor and the thirdsemiconductor material is a second chemical species of semiconductordifferent than the first chemical species of semiconductor.